CV

General Information

Full Name Arani Roy
Affiliation Purdue University · School of Electrical and Computer Engineering
Position Graduate Research Assistant / Fellow
Advisor Prof. Kaushik Roy
Email roy173@purdue.edu
Languages English (proficient), Bengali (native), Hindi

Research Interests

  • Controllable and geometry-aware generative models.
  • Machine unlearning and model editing across diffusion models and language models.
  • Efficient generative AI, diffusion-model compression, and efficient reasoning.
  • Backpropagation-free and local learning.
  • Multimodal foundation models, representation geometry, and model- and task-aware data curation.
  • Trustworthy machine learning.

Education

  • Aug 2021 — Dec 2026 (Expected) West Lafayette, IN
    Ph.D. in Electrical and Computer Engineering
    Purdue University
    • GPA: 3.8/4.0
    • Advisor: Prof. Kaushik Roy
  • 2014 — 2018 Kolkata, India
    B.E. in Electronics and Telecommunication Engineering
    Jadavpur University
    • GPA: 9.35/10.0

Experience

  • Aug 2021 — Present West Lafayette, IN
    Graduate Research Assistant / Fellow
    C-BRIC / NRL Lab, Purdue University
    • Developed HEART, a training-free geometry-aware framework for controllable diffusion generation using hyperspherical text-representation geometry and Kent-representation traversal; published at NeurIPS 2026.
    • Developed CURE, a fast training-free concept-unlearning framework using closed-form cross-attention weight editing with orthogonal projection and spectral representation geometry; published at NeurIPS 2025 as a Spotlight.
    • Developed SlimDiff, an activation-guided, timestep-aware diffusion compression framework using operator-aware low-rank decomposition; achieved 35% faster inference and approximately 100M parameter reduction while preserving generation quality.
    • Developed backpropagation-free local-learning methods combining Direct Feedback Alignment with structured low-rank geometry; work appeared at CVPRW 2025 and WACV 2026, where it was presented as an Oral and received the Best Student Paper – Algorithms Award.
    • Developed hardware-algorithm co-design methods for efficient neural networks, demonstrating approximately 3.5× energy savings and 1.3× speedup while maintaining model accuracy; published at ISCAS 2025.
    Projects Publications
  • May 2023 — Aug 2023 Dallas, TX
    Compute-in-Flash Research Intern
    Texas Instruments · Kilby Labs
    • Prototyped a digital compute-in-flash architecture for neural-network matrix-vector workloads and ported a 65 nm design to 28 nm flash, analyzing energy-throughput trade-offs.
  • Jul 2018 — Jul 2021 Bengaluru, India
    Associate Staff Engineer
    Samsung Semiconductor India R&D
    • Led library-design projects across 4 nm–130 nm technology nodes and automated design flows for approximately 2× faster turnaround.
    • Designed PPA-optimized sequential circuits resulting in three patents and the Samsung President's Award.
  • May 2017 — Jul 2017 Bengaluru, India
    Student Trainee
    Samsung Electronics
    • Developed a synthesizable memory compiler with an RTL-to-GDS flow, resulting in the Best Intern Project award.

Selected Publications

Honors & Awards

  • 2026
    Best Student Paper Award — Algorithms
    IEEE/CVF WACV
    • {"Awarded for \"Feedback Alignment Meets Low-Rank Manifolds"=>"A Structured Recipe for Local Learning\"; paper presented as an Oral at WACV 2026."}
  • 2026
    Bilsland Dissertation Fellowship
    Purdue University
    • Fellowship awarded for Fall 2026.
  • 2025
    NeurIPS Spotlight
    NeurIPS
    • CURE: Concept Unlearning via Orthogonal Representation Editing in Diffusion Models.
  • 2021
    Frederick N. Andrews Fellowship
    Purdue University
    • Awarded in 2021.
  • Samsung President's Award
    Samsung Semiconductor India R&D
    • Recognition for innovation in 4 nm / 5 nm circuit design.
  • 2017
    Samsung Best Intern Project Award
    Samsung Electronics
  • Best Paper — User Design Track
    33rd International Conference on VLSI Design & Embedded Systems
  • Sanghamitra Gold Medal
    Jadavpur University

Patents / Intellectual Property

  • Filed Nov 2020
    A True Single-Phase Clock (TSPC) NAND-based reset flip-flop
    Samsung Electronics · Indian application IN 202041052095 · U.S. Patent 11,569,799
    • Area- and power-efficient reset-function modification to a TSPC NAND-based flip-flop; the LinkedIn patent description reports approximately 15% power reduction and 10% area reduction relative to the referenced NAND-based architecture.
  • Filed Dec 2019
    Performance-optimized flip-flop with negative setup time
    Samsung Electronics · Indian application IN 201941051311 · U.S. Patent 11,362,648
    • {"U.S. grant title"=>"Pre-discharging based flip-flop with a negative setup time."}
  • Filed Dec 2019
    A TSPC edge-triggered pre-charge based flip-flop
    Samsung Electronics · Indian application IN 201941051135 · U.S. Patent 11,366,161
    • True Single Phase Clock pre-charge based flip-flop architecture for faster data arrival and optimized sequential-cell operation.

Technical Strengths

Research Diffusion Models, Diffusion Language Models, Large Language Models, Multimodal Foundation Models, Model Editing and Unlearning, Representation Geometry, Model Compression, Efficient Reasoning, Backpropagation-Free Learning, Trustworthy ML
ML / AI PyTorch, Hugging Face Transformers, Diffusers, CUDA, NumPy, Scikit-learn
Programming Python (proficient), C++, Bash, Java
Hardware / EDA Verilog, HSPICE, Cadence Virtuoso, Synopsys ICC2, FineSIM

Academic Service

  • Reviewer Service: NeurIPS 2026, ICML 2026, ECCV 2026, CVPR 2026, ICLR 2026, NeurIPS 2025, ICLR 2025, WACV 2026, ICCV 2025.